1. Field of the Invention
The present invention relates to a delay locked loop (hereinafter denoted with DLL), and more particularly to, a mode generator as a DLL control circuit.
2. Discussion of Related Art
Synchronous semiconductor devices operating in sync with an external clock generate an internal clock by using a clock buffer and a clock driver, so that the internal clock is generally delayed for a predetermined time, comparing with the external clock. As a result, an operation performance of a semiconductor device is degraded. That is, it causes a problem that a data access time tAC of the semiconductor device increases as long as a predetermined delay time by a clock buffer in a chip. Accordingly, it is necessary to comprise an internal clock generation circuit in a chip synchronizing with an external clock and a DLL is used as the internal clock generation circuit.
FIG. 1 is a block diagram illustrating a configuration of a general DLL.
A clock buffer 101 outputs an internal clock clkin and a reference clock ref_clk by inputting an external clock signal ext_clk. A DLL controller 102 controls an operation of the DLL by inputting a plurality of control signals control. A clock generator 103 generates a signal for controlling the DLL according to an adjustment of the DLL controller 102 and especially, generates a control signal pden toggling once for every seven clock. A phase detector 104 compares a feedback clock fb_clk outputted through a reference clock ref_clk outputted from the clock buffer 101, a delay line 100 and a replica delay model 112, and then outputs a control signal lag1 in response to the comparison result. A mode generator 105 decides whether or not phases of the reference click ref_clk and the feedback clock fb_clk are aligned according to the control signal pden outputted from the clock generator 103 and the control signal lag1 outputted from the phase detector 104, and then outputs a locked state signal lock_state. A phase sampler 106 inputs the control signal lag1 outputted from the phase detector 104 and then decides a clock rising state thereof for every seven clock. A delay line controller 107 controls first and second delay controllers 108, 109 according to the locked state signal lock_state outputted from the mode generator 105 and an output signal of the phase sampler 106. The first and second delay controllers 108, 109 respectively control a first delay line 110 and a second delay line 111 comprising the delay line 100 and thus adjunt a delay time thereto. The first delay line 110 inputs an internal clock clkin from the clock buffer 101, and delays the internal clock clkin for a predetermined time according to an output signal of the first delay controller 108. The second delay line 111 finely delays a first delayed signal through the first delay line 110. A replica delay model 112 inputs the feedback clock fb_clk to the phase detector 104 by modeling a path up to outputting data in response to the DLL clock in the DRAM. An output driver 113 is comprised of a rising clock driver and a falling clock driver, and thus outputs a clock signal outputted through the DLL.
FIG. 2 is a circuit diagram illustrating a mode generator of the conventional DLL control circuit and FIG. 3 is a waveform diagram illustrating a mode generator during a normal operation. With reference to the FIGS. 2 and 3, it will be described about a method of driving the conventional mode generator as follows.
When a reset signal reset is applied to high level, a first inverter I21 inverts it to low level. A first PMOS transistor P21 is turned on according to a low level output signal of the first inverter I21. Accordingly, a potential of a first node Q21 maintains high level, and the potential of the first node Q21 is inverted by a latch 21, fourth and fifth inverters I24, I25, and then the potential of the first node Q21 is outputted as a locked state signal lock_state in an initial state. After the reset signal reset is applied to low level and then the first PMOS transistor P21 is turned off, a third NMOS transistor N23 is driven according to the first control signal lag1. Here, the level of the first control signal lag1 is decided in response to the result comparing the reference clock ref_clk with the feedback clock fb_clk by means of the phase detector. If the feedback clock fb_clk is low level when the reference clock ref_clk is rising, the first control signal lag1 maintains high level. On the other hand, if the feedback clock fb_clk is high level when the reference clock ref_clk is rising, the first control signal lag1 maintains low level. Furthermore, a fourth NMOS transistor N24 is driven by the second control signal pden toggling once for every seven clock by being outputted from the clock generator. The second control signal pden is inverted through a seventh inverter I27. When the second control signal pden is transited from high level to low level, the seventh inverter I27 inverts the second control signal pden to high level. When the second control signal pden is transited from high level to low level, the signal generator 22 is driven. As a result, the signal generator 22 outputs a third control signal lag1_preb driving the second NMOS transistor N22 by using the first control signal lag1. When the first control signal lag1, the second control signal pden, and the third control signal lag1_preb are all high level, it means that each rising of the reference clock ref_clk and the feedback clock fb_clk is identical each other. During this, the second, third, and fourth NMOS transistors N22, N23, N24 are all turned on, and thus a potential of the first node Q21 becomes low level. The low level potential of the first node Q21 is outputted as a high level locked state signal lock_state through the latch 21, and the fourth and fifth inverters I24, I25. On the other side, when the locked state signal lock_state is low level, the feedback clock fb_clk is continually delayed until the reference clock ref_clk and the feedback clock fb_clk are identical each other and then is performed for shift right.
However, the conventional mode generator may cause a failure due to a charge sharing as shown in FIG. 4, when a layout or a size of a transistor is not correctly set. Referring to FIG. 4, while the feedback clock fb_clk is continually performing shift right, when the reference clock ref_clk and the feedback clock fb_clk have opposite phases each other, the first control signal lag1 becomes low level. Also, when the second control signal pden is transited to low level, the third control signal lag1_perb becomes high level and then the second NMOS transistor N22 is turned on. As the second NMOS transistor N22 is turned on and the third NMOS transistor N24 is turned off, the charge sharing is occurred between the first node Q21 and a second node Q22. Accordingly, when a potential of the first node Q21 falls down as low as inverted through the second inverter 122, although the phases of the reference clock ref_clk and the feedback clock fb_clk are inverted, it causes a failure that the locked state signal lock_state is outputted to high level (A).
FIG. 5 is a waveform diagram illustrating a failure possible to occur due to a feedback clock fb_clk noise. In this case as well, it can be occurred in the condition that the reference clock ref_clk and the feedback clock fb_clk have opposite phases each other. B in FIG. 5 denotes a waveform possible to occur due to the noise. When the reference clock is rising, the feedback clock fb_clk becomes high level by the noise (B). When the second control signal pden is transited from high level to low level, the third control signal becomes high level. Moreover, when the first control signal lag1 becomes high level due to an error of the feedback clock fb_clk at a timing that the second control signal pden becomes high level after seven clock, the second to fourth NMOS transistors N22 to N24 are all turned on. As a result, it is occurred that the locked state signal lock_state is outputted to high level by considering the DLL as being locked (C).
As aforementioned, the problems can be occurred in a specific frequency or voltage during a DRAM operation, which causes decrease of yield for a device. In order to solve those problems, a failure should be detected by performing a test for a specific frequency possible to occur a failure, and a layout of a circuit should be changed according to the detected failure.